In the design of modern electronic systems, it is increasingly common for large blocks of circuitry to be incorporated into custom integrated circuits known as ASICs, or Application Specific Integrated Circuits. These circuits are typically designed with the assistance of computer-aided engineering (CAE) tools. The actual process of design is such that the designer will use a graphics-based workstation to "draw" schematics of a circuit on the workstation's display screen. This is accomplished by positioning and interconnecting a number of pre-defined circuit elements. Such circuit elements are represented on the display screen by schematic symbols, but also have further, lower level circuit representations associated with them. For example, a logic AND gate may be represented on the designer's display screen as a three terminal device having two inputs and one output. At a lower level, however, there is a representation of that AND gate in the form of a transistor circuit comprising transistors, resistors, etc. It is in this form, that the circuit will actually exist on an integrated circuit when it is completed.
In order for a designer to be certain that his circuit will perform correctly when it is transformed into an ASIC, it is essential that accurate circuit simulation capability be available during the design process. Such simulations must take into account circuit delays, timing dependencies, loading characteristics, and layout induced effects such as parasitic capacitances, etc. These simulations are usually provided in the form of logic and timing models, which allow the designer to closely approximate the performance of his circuit when it is subjected to the stimuli that he specifies. The more accurate the simulation models, the higher the designer's confidence level that the circuit will perform as planned.
A number of tools exist which facilitate the task of ASIC design. Among these are a number of different types of simulators. Each type of simulator operates on a circuit description at a different level of abstraction.
The lowest level simulator is a circuit simulator. One such simulator is SPICE, available under a number of trade names from a number of different vendors. SPICE is a "standard" simulator, which has grown into a de-facto industry standard over a number of years. All SPICE simulators model circuits and their interconnections in the same way, and as such produce very similar results. One commercially available SPICE simulator is HSPICE, produced by Meta-Software Incorporated.
Circuit simulators, such as SPICE and its many variants, model a circuit in very great detail. All circuit elements are modeled in an analog fashion, and transistor models are very complete, taking into account many of the actual physical characteristics of the device. Voltages and currents are modeled as continuously variable entities, rather than the simple one-zero modeling of digital simulators. As a result, circuit-level model results are extremely accurate and highly representative of the performance of actual circuits. Very accurate information about propagation delays and effects of loading, parasitic capacitances, etc., may be derived from circuit-level simulators. Unfortunately, the extreme level of detail used in circuit-level simulation requires a very large number of calculations and restricts their practical use to smaller circuits, or where extremely detailed and accurate information is required.
Switch-level simulators attempt to provide fairly detailed and accurate simulations of digital circuits by modeling all of the transistors in a circuit as switches which may be either closed or open. While this type of model does not deal well with the effects of transistor parameters, for many types of digital logic it provides a reasonably accurate approximation with significantly fewer calculations required than for circuit-level simulators. As a result, fairly detailed and accurate simulation results may be obtained in far less time than is required for circuit level simulation. One commercially available switch-level simulator is TIMEMILL, produced by EPIC Design Technology, Incorporated.
Gate-level simulators are one level of abstraction further away from the circuit than switch-level simulators. Such simulators model a circuit as a group of interconnected logic gates. The logical functions are simple enough to perform, but propagation delays and timing relationships are handled in the form of lumped parameters. Some such simulators will attempt to account for the approximate effects of loading by applying simple equations for propagation delay where the delay is a function of the number of connections. Further, parameters may be passed back from detailed simulations whereby the effects of parasitic capacitances may be approximated, again in the form of a lumped parameter. Gate-level simulators run extremely fast compared to either circuit-level or switch-level simulators, due to the smaller number of calculations required. Provided that the lumped parameters are calculated properly, gate level simulators can provide very reasonable approximations of actual circuit performance. LSI Logic and Mentor Graphics are both commercial sources of gate-level simulators.
One other tool which is commonly made available by vendors of CAE stations and software is timing verification. Timing verification is performed by software which analyzes the timing relationships between logic state changes within a circuit and determines if certain timing criteria such as minimum set-up and hold times have been violated. Timing verifiers do not attempt to model the circuit as it would operate, but rather attempt to analyze the circuit's behavior in the form of relative delays, and cause and effect relationships within a circuit.
Because of the size and complexity of circuits which are commonly put into ASICs, it is essential to the designer that circuit simulations run fast. For this reason, logic simulation of ASICs by the designer is performed almost exclusively through the use of gate-level simulators. In order for gate-level simulation to provide reasonably accurate approximations of actual circuit performance, a fairly extensive process of analysis, simulation and model preparation is required of the tool vendor.
The process of generating logic and timing models for a new circuit element, e.g., gate, flip-flop, adder, etc., is typically a lengthy, labor-intensive process whereby schematics are drawn at both the logic-level and circuit-level. A circuit-level model is generated from the circuit-level (transistor circuit) schematic by means readily available in the present art, usually automatically. The logic circuit and transistor circuits are then analyzed to determine what stimuli should be applied to the circuit level model to arrive at simulation results which will give best indication of the delay characteristics of the circuit. The circuit is laid out and an analysis is performed to determine the effect of adjacent wire runs, etc., on the overall performance of the circuit. The circuit-level simulation is run under several different simulated conditions of power supply voltage and temperature to determine worst and best case delay characteristics, rise and fall times, etc.
The simulation results are examined to determine from the difference in time between critical stimuli and output transitions what values of propagation delay, etc., should be used for the purpose of logic modeling. The logic diagram is annotated with these values in the form of attributes which can be read and acted upon by a logic simulator. Layout induced effects are taken into account, the delay values are altered accordingly, and the logic model is complete.
Timing verification models are usually generated manually based upon data derived from the simulation run and also on knowledge of circuit function and topology. Some logic simulators, such as MDE from LSI Logic Incorporated, combine the functions of logic simulation and timing verification into a multi-mode modeler.
Once a model has been generated, it is common practice to compare the results of circuit-level, switch-level, and gate-level simulations to verify that the results track one another closely. This process is known as model verification. If the models do not track closely enough, the user of a logic simulator will not get accurate representations of the performance of his design, reducing overall confidence that the circuit will perform correctly when it is incorporated into an ASIC.
In the present art, all of the aforementioned simulation, analysis, and parameter extraction operations are performed manually by human operators. Very often, many different people perform different steps in the process, due to the many sets of skills required.
Because of the labor-intensive nature of logic/timing model generation and because of the rapid rate of change in the field of digital electronics, it becomes extremely desirable to have a method of automating the process so that accurate logic and timing models may be generated quickly enough to keep up with the needs of the design community, without requiring large, dedicated, highly-trained staffs.
In the foregoing discussion, it was noted that various levels of simulation can be performed at various levels of abstraction. Some of the levels discussed included circuit-level simulation, switch-level simulation and gate-level simulation. Each type of simulation models an electronic design at a different level of abstraction. Circuit-level simulation, which is the most detailed of those discussed hereinabove, models an electronic design in terms of its smallest components, transistors. Switch-level simulation moves a level of abstraction away from the circuit-level by modeling transistors as idealized switches (a fair approximation for logic circuits). Gate-level simulation describes an electronic design as a series of interconnected logic functions.
Further levels of abstraction are possible. For example, it is possible to model a digital electronic design in terms of its "behavior". That is, a digital electronic design can be described in terms of its response to external stimulus, i.e., its behavior. Present day state-of-the-art design technique, logic synthesis, is really only a mapping between different levels of physical abstraction.
One of the most difficult problems in design automation is the inability to get timing closure at even the gate level effectively. This forces designers to do two designs: logic design and timing design. Otherwise, the designer simply over-designs the circuits, because the best case timing is much different from the worst case timing. In other cases, designers insist on control of device layout so that they can evaluate all of the tradeoffs between implementation and timing.
Present computer aided design (CAD) systems for the design of electronic circuits, referred to as ECAD or Electronic CAD systems, assist in the design of electronic circuits by providing a user with a set of software tools running on a digital computer with a graphical display device. Typically, five major software program functions run on the ECAD system: a schematic editor, a logic compiler, a logic simulator, a logic verifier, and a layout program. The schematic editor program allows the user of the system to enter and/or modify a schematic diagram using the display screen, generating a net list (summary of connections between components) in the process. The logic compiler takes the net list as an input, and using a component database puts all of the information necessary for layout, verification and simulation into a schematic object file or files whose format(s) is(are) optimized specifically for those functions. The logic verifier checks the schematic for design errors, such as multiple outputs connected together, overloaded signal paths, etc., and generates error indications if any such design problems exist. The logic simulator takes the schematic object file(s) and simulation models, and generates a set of simulation results, acting on instructions initial conditions and input signal values provided to it either in the form of a file or user input. The layout program generates data from which a semiconductor chip (or a circuit board) may be laid out and produced.
The Modular Design Environment (MDE) produced by LSI Logic Corporation of Milpitas, California, is a suite of software tools for computers running the UNIX operating system. MDE comprises a schematic editor (LSED) and a simulator (LDS), among other software programs, and provides an example of commercially available tools of the aforementioned type. Another example of a schematic editor, schematic compiler, and schematic simulator may be found in the SCALDstation produced by Valid Logic Systems, Inc. of Mountain View, Calif.
VHDL, or VHSIC (Very High Speed Integrated Circuit) Hardware Description Language, is a recently developed, higher level language for describing complex devices. The form of a VHDL description is described by means of a context-free syntax together with context-dependent syntactic and semantic requirements expressed by narrative rules. VHDL is described in IEEE Standard VHDL Language Reference Manual (IEEE Std 1076-1987), and is also known as MIL-STD-454, Regulation 64.
VHDL represents an important step forward in design specification languages because the semantics, or intent, of the language constructs are clearly specified. In theory, VHDL unambiguously describes a designer's intended system or circuit behavior, in syntactic terms. The "design entity" is the primary hardware abstraction in VHDL. It represents a portion of a hardware design that has well-defined inputs and outputs and performs a well-defined function. A design entity may represent an entire system, a sub-system, a board, a chip, a macro-cell, a logic gate, or any level of abstraction in between. A "configuration" can be used to describe how design entities are put together to form a complete design.
VHDL supports three distinct styles for the description of hardware architectures. The first of these is "structural" description, wherein the architecture is expressed as a hierarchical arrangement of interconnected components. The second style is "data-flow" description, in which the architecture is broken down into a set of concurrent register assignments, each of which may be under the control of gating signals. This description subsumes the style of description embodied in register transfer level (RTL) descriptions. The third style is "behavioral" description, wherein the design is described in sequential program statements similar to a high-level programming language. In the main hereinafter, the behavioral description style is discussed. However, all three styles may be intermixed in a single architecture.
A methodology for deriving a lower-level, physically-implementable description, such as a RTL description of the higher level (e.g. VHDL) description, via an intermediate rule-based tool such as Prolog, is disclosed herein.
Prolog is a programming language based on predicate logic. It can be used for "intelligent" tasks like mathematical theorem proving. A Prolog program is a set of rules which define the relationships among objects. The general form of a Prolog rule is a "horn" clause, in which a specified "goal" is true if certain conditions are true. Execution of a Prolog program involves finding a proof for the goal in question, using unification and resolution. An important aspect of Prolog employed in the present invention is "term.sub.-- expansion", which converts pre-defined rules into ordinary Prolog clauses.